Sr. Physical Design Engineer
Bangalore, Ahmedabad, US
Job Description
As a Senior Physical Design Engineer, you will be working on full chip integration and the timing & physical aspect of multi-million gate ASICs. This includes floor-planning, generating timing constraints, generating timing models for custom blocks, performing timing driven P&R, static timing analysis, deriving timing closure using various strategies e.g. buffer resizing, repeater insertion, etc., performing clock tree insertion and clock skew analysis, creating power distribution scheme, analyzing IR-drop, signal integrity of the whole chip.
We are looking for
3-5 years of extensive experience in large VLSI physical design implementation on 0.18u or below technology. Must have hands on experience of chip tapeouts including Physical Verification, Decks (DRC/LVS/ERC/Antenna) & Tape out. Must have solid experience on Magma/Cadence/Synopsys tool suite (P&R, physical extraction and verification, timing verification, etc.)
The following will be a plus
Some experience with synthesis, timing analysis and DFT is desired. Experience with Calibre and Spice is a plus
Interested
Send your resume to ankit.desai@einfochips.com Quote job code EDAIndia.com-802007and the position that you are applying for in the subject line e.g.
Subject:EDAIndia.com-802007, Application for the post of Sr. Physical Design Engineer
Quote job code EDAIndia.com-36297144 and the position that you are applying for in the subject line e.g.
Subject:EDAIndia.com-36297144, Application for the post of Sr. Physical Design Engineer
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