Welcome, Guest. Please
Login
or
Register
.
EDAIndia: Chip design discussion board
Sep 9
th
, 2010, 8:42pm
Edainda Discussion Board
›
Tools
›
Synthesis Tools
(Moderator:
YaBB Administrator
)
‹
Previous topic
| No topic ›
Pages: 1
Moved: VLSI Training @ TTM (TIIT), Bangalore (Read 988 times)
YaBB Administrator
YaBB Administrator
Posts: 10
Gender:
Moved: VLSI Training @ TTM (TIIT), Bangalore
Mar 5
th
, 2007, 4:32pm
This topic has been moved to
Training in embedded and VLSI
by YaBB Administrator.
Back to top
«
Last Edit: Apr 22
nd
, 2007, 10:50pm by YaBB Administrator
»
The Administrator.
Remembering world events according to internal chip milestones
IP Logged
Pages: 1
Edainda Discussion Board
›
Tools
›
Synthesis Tools
(Moderator:
YaBB Administrator
)
‹
Previous topic
| No topic ›
Forum Jump:
-----------------------------
Languages
-----------------------------
- Perl for eda
- verilog
- VHDL
- Verification
-----------------------------
Tools
-----------------------------
=> Synthesis Tools
- Verification Tools
- Other scripts and tools
-----------------------------
Site Design
-----------------------------
- EDAIndia Community Development
- Discussion on the monthly Newsletter
- The Free online Bookshelf Discussion
-----------------------------
Technology
-----------------------------
- ASIC
- FPGA
-----------------------------
Design Flow
-----------------------------
- Design for testability
-----------------------------
Misc
-----------------------------
- Companies
- Head hunters and job board
- Misc
- Training in embedded and VLSI
-----------------------------
Backend
-----------------------------
Edainda Discussion Board
» Powered by
YaBB 2.1
!
YaBB
© 2000-2005. All Rights Reserved.
Pages: 1
Moved: VLSI Training @ TTM (TIIT), Bangalore (Read 988 times)
Pages: 1
Pages: 1
Moved: VLSI Training @ TTM (TIIT), Bangalore (Read 988 times)
Pages: 1
