VHDL is a language designed by a committee. It is verbose, enforces strict type checking, is mostly used in Europe and is the preferred language of instruction in Indian academic environment. VHDL is an acronym which stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language.
VHDL Related discussions are normally taken to the usenet group comp.lang.vhdl This groups was formed with the following charter
"The newsgroup comp.lang.vhdl was created in January 1991. It's an international forum to discuss ALL topics related to the language VHDL which is currently defined by the IEEE Standard 1076/93. Included are language problems, tools that only support subsets etc. but NOT other languages such as Verilog HDL. This is not strict - if there is the need to discuss information exchange from EDIF to VHDL for example, this is a topic of the group. The group is unmoderated. Please think carefully before posting - it costs a lot of money! (Take a look into your LRM for example or try to search http://www.Deja.com/usenet - if you still cannot find the answer, post your question, but make sure, that other readers will get the point)."Other places to discuss design issues are the edaindia mailing list email@example.com and the VHDL section of the EDAIndia forum
Decent netzians always check wether a question has been previously asked and answered, before asking it...
So here is the official Frequently Asked Questions
The VHDL FAQ - This FAQ is divided into 4 sections and is posted monthly to the VHDL Newsgroup
Part 1: FAQ General (contacts, etc.)
Part 2: Lists of Books on VHDL
Part 3: Lists of Products & Services (Freewares and Commercial stuff)
Part 4: Glossary.