Low Power ASICS can be built using a mix of various techniques. These techniques are applicable at various design stages.img 1)
- Power Efficient Architecture
- Clock Gating
- Power Gating
- Frequency Scaling
- Voltage Scaling
- Transistor threshold
- Back Biasing
- Reduce Oxide Thickness
- FINFET
- Power efficient circuits
- Parallelism in micro-architecture
Dynamic Power Reduction # Clock Gating # Power efficient circuits # Variable frequency # Variable voltage supply
Leakage Power Reduction # Minimize usage of Low Vt Cells # Power Gating # Back Biasing # Reducing Dynamic Power # Reduce Oxide Thickness # Use FINFET’s
- Process selection: Process with High VT have lower power consumption. Check with your fab vender to findout the process for your technology node which gives the lower power.
- Architecture Architecture decisions involve tradeoffs between various design parameters if low power is a major concern for your design lean towards the architecture which would consume low power.
- Implementation Implementation decisions can also affect power consumption. e.g. selection of gray-coded FSM state variables, logic activity based clock network switching etc.
- Backend Backend tools implement various techniques to improve the power numbers e.g. logic activity based clock gating etc.
