Open Source ASIC Design

For decades the EDA landscape was dominated by the big 3. There were some attempts to develop opensource EDA tools, but these were playthings for teaching purpose. Not something that can actually be used by the industry.

In the past few years the landscape started changing.

• Version 10.x of Icarus Verilog and GTK Wave gave a nearly complete verilog-2000 simulator.
• GHDL evolved into a good VHDL simulator with its support for VHDL 2008
• Verilator became the fastest multithreaded simulator beating out even the big 3 in speed benchmarks.
• Bluespec Opensourced its bsv compiler providing a HLS tool
• The RISCV ecosystem renewed interest in the EDA tool chain and we started getting new Hardware construction languages like Chisel, tools like Rocket Chip and Diplomacy and dozens of free 32 and 64 bit processor implementation.
• cocotb got a new breath of life in 2019 as the community started contributing to it and has today evolved into a robust compititor to other verification frameworks.
• Yosys because a usable basic synthesis tool.
• RTL to GDSII flows like qflow and openRoad started integrating various backend tools (synthesis, timing closure, placement layout, routing etc) to create an end to end design flow.
• Symbiflow is creating backend tools on the FPGA front.
• FOSSi has been conducting ORConf since the start of this decade which see's presence from across the ecosystem.

These toolsets resulted in evolution of ASIC design services companies like Dyumnin Semiconductors which use opensource tools to provide Design, Verification and Validation services to Early Stage Startup's.

A Complete design workflow based around free/Opensource tools allows the Silicon Startup to have the same burn rate as a software startup and to prototype their idea and bring their design close to tapeout without burning a singnificant portion of their investment in EDA Tools.

Investment in Silicon startup's had nearly dried out in the past decade as the investment in a Silicon Startup was more than 10 times the investment in any other startup. An Entrepruner might have an innovative idea or algorithm which may at most take a few hundred thousands of gates. But in order to make a viable complete product he requires over a dozen other components(e.g. processor, memory controller, communication IP's, NOC etc.) Each requiring a license fee running in 100K+

Even though the mask costs run in millions, the cost of IP's, EDA tools, Design and verification outweigh the mask cost by a factor of up to 10. To some extent OpenCores helps bridge the IP Gap.

The support Question.

A Major problem with open source tools is support. While iverilog and gtkwave are healthy projects. The university projects built around them like covered and Vermin suffer from "bit rot". e.g.

• The language support may be incomplete or outdated.
• The libraries used by the tools may have incompatabile dependencies with the latest OS.
• In most cases the original developer presented his thesis, got his degree, and over time lost interest.

In such cases unless someone steps up to own the code base and maintain it, the project overtime becomes useless.

An ecosystem where a university or a commercial company is willing to support and extend Opensource IP's will reduce the cost of bringing a new chip to the market.