The commonly used sign off simulators are
Modelsim from mentor graphics.
nc-vhdl from cadence.
vcs from synopsys.
Free VHDL simulators are here
 vanilla cad tools + the related waveform viewer for linux and VHDL Simili
The freehdl and gnu eda are projects which are expected to provide opensource development tools. I have not seen any significant offering from these projects in since 2000 so dont wait for them.